In the fabrication of light-emitting diodes (LEDs) and other high-performance devices such as laser diodes, optical detectors, and field effect transistors, a chemical vapor deposition (CVD) process is typically used to grow a thin film stack structure using materials such as gallium nitride over a sapphire or silicon substrate. A CVD tool includes a process chamber, which is a sealed environment that allows infused gases to be deposited upon the substrate (typically in the form of wafers) to grow the thin film layers. An example of a current product line of such manufacturing equipment is the TurboDisc® family of MOCVD systems, manufactured by Veeco Instruments Inc. of Plainview, N.Y.
A number of process parameters are controlled, such as temperature, pressure and gas flow rate, to achieve a desired crystal growth. Different layers are grown using varying materials and process parameters. For example, devices formed from compound semiconductors such as III-V semiconductors typically are formed by growing successive layers of the compound semiconductor using metal organic chemical vapor deposition (MOCVD). In this process, the wafers are exposed to a combination of gases, typically including a metal organic compound as a source of a group III metal, and also including a source of a group V element which flow over the surface of the wafer while the wafer is maintained at an elevated temperature. Typically, the metal organic compound and group V source are combined with a carrier gas which does not participate appreciably in the reaction as, for example, nitrogen. One example of a III-V semiconductor is gallium nitride, which can be formed by reaction of an organo-gallium compound and ammonia on a substrate having a suitable crystal lattice spacing, as for example, a sapphire wafer. Typically, the wafer is maintained at a temperature on the order of 1000-1100° C. during deposition of gallium nitride and related compounds.
In a MOCVD process, where the growth of crystals occurs by chemical reaction on the surface of the substrate, the process parameters must be controlled with particular care to ensure that the chemical reaction proceeds under the required conditions. Even small variations in process conditions can adversely affect device quality and production yield. For instance, if a gallium and indium nitride layer is deposited, variations in wafer surface temperature will cause variations in the composition and bandgap of the deposited layer. Because indium has a relatively high vapor pressure, the deposited layer will have a lower proportion of indium and a greater bandgap in those regions of the wafer where the surface temperature is higher. If the deposited layer is an active, light-emitting layer of an LED structure, the emission wavelength of the LEDs formed from the wafer will also vary to an unacceptable degree.
In a MOCVD process chamber, semiconductor wafers on which layers of thin film are to be grown are placed on rapidly-rotating carousels, referred to as wafer carriers, to provide a uniform exposure of their surfaces to the atmosphere within the reactor chamber for the deposition of the semiconductor materials. Rotation speed is on the order of 1,000 RPM. The wafer carriers are typically machined out of a highly thermally conductive material such as graphite, and are often coated with a protective layer of a material such as silicon carbide. Each wafer carrier has a set of circular indentations, or pockets, in its top surface in which individual wafers are placed. Typically, the wafers are supported in spaced relationship to the bottom surface of each of the pockets to permit the flow of gas around the edges of the wafer. Some examples of pertinent technology are described in U.S. Patent Application Publication No. 2012/0040097, U.S. Pat. No. 8,092,599, U.S. Pat. No. 8,021,487, U.S. Patent Application Publication No. 2007/0186853, U.S. Pat. No. 6,902,623, U.S. Pat. No. 6,506,252, and U.S. Pat. No. 6,492,625, the disclosures of which are incorporated by reference herein.
The wafer carrier is supported on a spindle within the reaction chamber so that the top surface of the wafer carrier having the exposed surfaces of the wafers faces upwardly toward a gas distribution device. While the spindle is rotated, the gas is directed downwardly onto the top surface of the wafer carrier and flows across the top surface toward the periphery of the wafer carrier. The used gas is evacuated from the reaction chamber through ports disposed below the wafer carrier. The wafer carrier is maintained at the desired elevated temperature by heating elements, typically electrical resistive heating elements disposed below the bottom surface of the wafer carrier. These heating elements are maintained at a temperature above the desired temperature of the wafer surfaces, whereas the gas distribution device typically is maintained at a temperature well below the desired reaction temperature so as to prevent premature reaction of the gases. Therefore, heat is transferred from the heating elements to the bottom surface of the wafer carrier and flows upwardly through the wafer carrier to the individual wafers. Also, the heat transferred upwards through the carrier material is radiated from the top surface of the wafer carrier. The degree of radiative emission from the wafer carrier is determined by the emissivity of the carrier and the surrounding components.
A great deal of effort has been devoted to system design features to minimize temperature variations during processing; however, the problem continues to present many challenges. For instance, wafers are significantly less thermally conductive than the wafer carrier. Introducing a sapphire wafer in a pocket of the wafer carrier creates a heat-trapping, or “blanketing” effect. This phenomenon results in a generally radial thermal profile at the pocket floor which is hotter in the center and lower temperature towards the outer radius of the pocket, where the heat can be emitted by radiation and convection into the environment.
Another effect that impacts thermal uniformity of the wafers in-process is the thermal gradient across the thickness of the wafer, which causes a concave bow, resulting in a non-uniform gap distance between the wafer bottom and pocket floor. This is because the hotter bottom of the wafer tends to expand more in relation to the colder top surface, thereby assuming a classical concave shape. The concave bow will generally add to the thermal non-uniformity that already exists on the wafer due to thermal blanketing effects. Due to the very small thermal conductance of the gas gap compared to the carrier material, the wafer surface temperature is extremely sensitive to changes in the gap magnitude. In the case of a concave bow, the center of the wafer will be closer to the pocket floor, and consequently hotter compared to the outer edges. This effect is more pronounced in larger-diameter wafers, which are typically made from silicon. Also, with silicon wafers in particular, the bowing is further aggravated by film stresses from a crystal lattice mismatch between the silicon substrate and the deposited layers used to fabricate the devices on the substrate.
A related thermal conduction transfer process also occurs in the lateral direction from wafer carrier pocket edge to the wafer edge, depending upon this distance. In CVD tools utilizing a high-speed rotating wafer carrier, the wafers are typically driven towards the outer edge of the pockets due to high centrifugal forces. Thus, these wafers are in typically in contact with the outer pocket edge. The non-concentric position of a wafer in the pocket creates a non-uniform gap from the pocket edge that is zero at the point of contact, and increases circumferentially away from the contact point. The smaller gap between the wafer and carrier in regions close to the point of contact increases the conductive heat transfer from the carrier to the wafer. This “close proximity” effect results in much higher edge temperatures in the region of contact. Co-pending U.S. patent application Ser. No. 13/450,062, the disclosure of which is incorporated by reference herein, describes approaches for reducing the proximity effect utilizing “bumpers” to center the wafer at a prescribed distance from the pocket edge. These bumpers have been shown to be successful in virtually eliminating the high temperature crescent generated by the proximity effect. However, several practical challenges remain, particularly
Another challenge in maintaining temperature uniformity over the wafers relates to the wafers, which are typically circular, flat discs, having one or more straight portions of their edge commonly referred to as “flats.” Flats are generally used to indicate the doping type of the wafer, as well as the crystallographic orientation of the wafer, and are typically found on wafers smaller than 200 mm. In CVD processing, however, the flats present a non-uniformity for heat transfer to the wafer. In particular, the heat transfer to the portion of the wafer near the flat tends to be reduced due to the separation between the edge of the wafer flat and the wafer carrier. Also, the flat introduces a variation in gas flow that also affects the temperature in the vicinity of the flat.
A further concern relates to multi-wafer pocket geometries with non-concentric pocket locations. Here, the thermal profile becomes more complicated as the convective cooling is dependent upon the historical gas streamline path passing over both the wafer carrier and wafer regions. For high-speed rotating disc reactors, the gas streamlines spiral outward from inner to outer radius in a generally tangential direction. In this case, when the gas streamline is passing over the exposed portion of the wafer carrier (such as the regions of “webs” between the wafers), it is heated up relative to the regions where it is passing over the wafers. In general, these webs are quite hot relative to the other regions of the carrier where the wafers are situated, as the heat flux streamlines due to the blanketing effect have channeled the streamlines into this region. Thus, the gas paths passing over the webs create a tangential gradient in temperature due to the convective cooling, which is hotter at the leading edge (entry of the fluid streamline to the wafer) relative to the trailing edge (exit of the fluid streamline over the wafer).
These effects contribute to a reduced product yield since devices fabricated from portions of the wafer near the flat tend to exhibit increased photoluminescence relative to the target value for the rest of the wafer. Solutions are needed that addresses one or more of these, and related, challenges in improving wafer heating uniformity in CVD reactors.